As one of the metal-oxide-semiconductor field-effect transistors (hereinafter referred to as the “MOSFET's”) having a trench-structure, a MOSFET having a field-plate structure including a field plate biased at a source potential and formed in the bottom of a trench, in which a gate electrode is formed, is known to the persons skilled in the art. Hereinafter, the field-plate structure described above will be referred to as a “vertical field-plate structure”. By providing a MOSFET with the vertical field-plate structure, the breakdown voltage will be lowered hardly, even if the impurity concentration in the drift region is high. Therefore, the ON-state voltage is reduced and the gate capacitance (parasitic capacitance) is reduced.
FIG. 16 is the cross sectional view of a conventional MOSFET having a vertical field-plate structure (hereinafter referred to as a “vertical-field-plate-type MOSFET”).
In the vertical-field-plate-type MOSFET shown in FIG. 16, n− drift region 102 is formed on n+ drain region 101. In n− drift region 102, an active area and an edge-termination area (not shown) surrounding the active area are formed. The edge-termination area functions to improve the breakdown voltage of the active area.
In the surface portion in the active area of n− drift region 102, p-type well region 103 is formed. In the surface portion of p-type well region 103, n+ source region 104 and p+ heavily doped region 105 are formed selectively. Trench 106 is formed through n+ source region 104 and p-type well region 103. Trench 106 is extended into n− drift region 102. In trench 106, field plate 108 is disposed with insulator film 107 interposed between field plate 108 and the trench 106 inner wall. Field plate 108 is connected electrically to a source electrode. In trench 106, gate electrode 110 is disposed above field plate 108 with gate insulator film 109 interposed between gate electrode 110 and the trench 106 side wall.
Field plate 108 is positioned on the n− drift region 102 side of the boundary between n− drift region 102 and p-type well region 103. Field plate 108 is insulated from gate electrode 110 by a first interlayer insulator film. Source electrode 112 is in contact with n+ source region 104 and p+ heavily doped region 105. Source electrode 112 is insulated from gate electrode 110 by second interlayer insulator film 111. Drain electrode 113 is disposed on an n+ drain region 101 surface opposite to the n+ drain region 101 surface, on which n− drift region 102 is formed. Drain electrode 113 is in contact with n+ drain region 101.
The following Patent Documents 1 and 2 propose vertical-field-plate-type MOSFET's as described below. The proposed vertical-field-plate-type MOSFET's include a GD-UMOSFET (graded-doped U-shape MOSFET) unit cell that includes an upper trench-based gate electrode and a lower trench-based source electrode. The use of the trench-based source electrode instead of a large gate electrode which occupies the entire trench reduces the gate-to-drain capacitance (COD) of the UMOSFET and thereby improves the switching speed by reducing the amount of gate charging and discharging current that is needed during high-frequency operations.
A MOSFET obtained by providing the drift region of the vertical-field-plate-type MOSFET (cf. FIG. 16) with a double-layer structure (not shown) is well known to the persons skilled in the art. In the double-layer structure, the impurity concentration in the drift region on the p-type well region side of the trench corner is set to be higher than the impurity concentration in the drift region on the drain region side of the trench corner. By providing the drift region with the double-layer structure as described above, the ON-state voltage is further reduced on the p-type well region side in the drift region. Moreover, the electric field is relaxed in the vicinity of the trench bottom surface, to which the electric field is liable to localization, on the drain region side in the drift region. Therefore, the breakdown voltage in the active area is prevented from lowering.
The following Patent Document 3 proposes a semiconductor device as described below that reduces the gate capacitance and improves the breakdown voltage.
The semiconductor device proposed in the Patent Document 3 includes a silicon wafer of a first conductivity type; trenches formed into the top surface of the wafer with a certain spacing between the trenches, the trench extending to a predetermined depth; an insulator coating lining the side wall and bottom of the trench; an electrically conductive gate body filling the trench; a channel region of a second conductivity type extending into the top of the wafer to a first depth shallower than the predetermined depth; a source region of the first conductivity type extending into the channel region to a second depth from the top of the wafer to define an invertable channel along the side of the trench in the channel region which extends between the first and second depths; a source electrode formed on the top surface of the wafer and connected to the source and channel regions; a drain electrode connected to the bottom of the wafer; and a shallow diffusion of the second conductivity type surrounding the bottom of the trench.
The shallow diffusion is doped more lightly than the channel region substantially. The shallow diffusion is depleted at all times by the built-in junction voltage at the junction thereof to the surrounding wafer material of the first conductivity type.
The following Patent Document 4 proposes a device as described below. The device proposed in the Patent Document 4 includes a first main electrode; a second main electrode; a drain region of a second conductivity type connected to the second main electrode; an epitaxial region of the second conductivity type on the drain region; a semiconductor base region of a first conductivity type above the epitaxial region; a trench formed through the semiconductor base region; a gate electrode in the trench with an insulator film interposed between the gate electrode and the inner wall of the trench; a source region of the second conductivity type formed in the surface portion of the semiconductor base region and in contact with the trench, the source region being connected to the first main electrode; a semiconductor region of the second conductivity type between the semiconductor base region and the epitaxial region; and a semiconductor region of the first conductivity type between the semiconductor region of the second conductivity type and the epitaxial region, the semiconductor region of first conductivity type being in contact with the semiconductor region of the second conductivity type.
In the device proposed in the Patent Document 4, the current flow between the first and second main electrodes caused by a voltage applied in a predetermined direction between the first and second main electrodes is controllable by a voltage applied to the gate electrode. In the state, in which the voltage applied in the predetermined direction is zero, the semiconductor region of the second conductivity type and the semiconductor region of first conductivity type are depleted completely. By the expansion of the depleted region to the surrounding of the trench bottom, the capacitance between the drain and source and the capacitance between the drain and gate are reduced.
The following Patent Document 5 proposes a device as described below. The device proposed in the Patent Document 5 includes a semiconductor substrate of a first conductivity type; a semiconductor layer of the first conductivity type on the semiconductor substrate, the semiconductor layer working as a drain region; a channel layer of a second conductivity type opposite to the first conductivity type formed on the semiconductor layer; a trench extending through the channel layer into the semiconductor layer; an insulator film on the inner wall of the trench; a gate electrode buried in the trench; a source region of the first conductivity type formed in the surface portion of the channel layer and in adjacent to the trench; and a lightly doped impurity region of the first conductivity type in the semiconductor layer, in which the bottom of the trench is positioned.
The following Patent Document 6 proposes a semiconductor device that relaxes the electric field in the vicinity of the trench bottom surface and prevents the breakdown voltage from lowering. The semiconductor device proposed in the Patent Document 6 includes a semiconductor body. The semiconductor body includes a first surface; a second surface; an internal region; an edge region in adjacent to the internal region; a first semiconductor layer of a first conductivity type extending through the internal region to the edge region; and one or more functional device zones of a second conductivity type complementary to the first conductivity type, the one or more functional device zones being in the internal region in the first semiconductor layer; and an edge structure positioned in the edge region.